Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10520549 | Semiconductor device, diagnostic test, and diagnostic test circuit | Yukitoshi Tsuboi, Hideo Nagano, Hiroshi Nagaoka, Yutaka Igaku, Naotaka Kubota | 2019-12-31 |
| 9810738 | Semiconductor device, diagnostic test, and diagnostic test circuit | Yukitoshi Tsuboi, Hideo Nagano, Hiroshi Nagaoka, Yutaka Igaku, Naotaka Kubota | 2017-11-07 |
| 7490271 | Semiconductor device mounting chip having tracing function | Motoki Higashida | 2009-02-10 |
| 7260893 | Method of attaching a transmission oil cooler to an aluminum tank | Chris Calhoun, Terry Joseph Hunt, David A. Southwick, Karl Paul Kroetsch, Krzysztof Wawrocki +2 more | 2007-08-28 |
| 7147040 | Heat exchanger with tank utilizing integral positioning guides | Chris Calhoun, Terry Joseph Hunt, David A. Southwick, Karl Paul Kroetsch, Krzysztof Wawrocki +2 more | 2006-12-12 |
| 7146543 | Semiconductor device mounting chip having tracing function | Motoki Higashida | 2006-12-05 |
| 7059050 | One piece integral reinforcement with angled end caps to facilitate assembly to core | Chris Calhoun, Terry Joseph Hunt, David A. Southwick, Karl Paul Kroetsch, Krzysztof Wawrocki +2 more | 2006-06-13 |
| 7007743 | Header tank with integral mounting flange | Chris Calhoun, Terry Joseph Hunt, David A. Southwick, Karl Paul Kroetsch, Krzysztof Wawrocki +2 more | 2006-03-07 |
| 6625799 | Technology mapping method and storage medium | — | 2003-09-23 |
| 5909374 | System and method for verifying logic circuit based on signal line set affecting internal signal | — | 1999-06-01 |
| 5734917 | System for producing combination circuit to satisfy prescribed delay time by deleting selected path gate and allowing to perform the permissible function for initial circuit | — | 1998-03-31 |
| 5535132 | Variable sequence determining method for a dichotomy determination graph | Masahiro Fujita | 1996-07-09 |
| 5490268 | Method for changing an arrangement of an initial combinational circuit to satisfy prescribed delay time by computing permissible functions of output gates and remaining gates | — | 1996-02-06 |
| 5461574 | Method of expressing a logic circuit | Masahiro Fujita | 1995-10-24 |