Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11132422 | Automating solving NP problems in annealer systems | Wei-Peng Chen | 2021-09-28 |
| 9813188 | Transmitting circuit, communication system, and communication method | Yuuki Ogata | 2017-11-07 |
| 9684332 | Timing control circuit | Yuuki Ogata | 2017-06-20 |
| 9160380 | Transmission circuit, communication system and transmission method | — | 2015-10-13 |
| 9049059 | Receiving circuit | Takanori Nakao | 2015-06-02 |
| 8836369 | Latch circuit, flip-flop circuit, and divider | Yuuki Ogata | 2014-09-16 |
| 8750430 | Data receiver circuit | — | 2014-06-10 |
| 8593313 | Parallel-to-serial conversion circuit, information processing apparatus, information processing system, and parallel-to-serial conversion method | — | 2013-11-26 |
| 8102288 | Data transmitting circuit and method | — | 2012-01-24 |
| 7561616 | System and method for equalizing high-speed data transmission | — | 2009-07-14 |
| 7512178 | Equalizing a signal for transmission | Yasuo Hidaka, Weixin Gai, Hirotaka Tamura | 2009-03-31 |
| 7427878 | Low-voltage differential signal driver for high-speed digital transmission | Jian Jiang | 2008-09-23 |
| 7173965 | Equalizing a signal for transmission | Yasuo Hidaka, Weixin Gai, Hirotaka Tamura | 2007-02-06 |
| 7065135 | System and method for equalizing high-speed data transmission | — | 2006-06-20 |
| 6898742 | System and method for automatic deskew across a high speed, parallel interconnection | Richard L. Schober, Raghu Sastry, Hirotaka Tamura | 2005-05-24 |
| 6636993 | System and method for automatic deskew across a high speed, parallel interconnection | Richard L. Schober, Raghu Sastry, Hirotaka Tamura | 2003-10-21 |
| 6493320 | Automatic initialization and tuning across a high speed, plesiochronous, parallel link | Richard L. Schober, Raghu Sastry, Hirotaka Tamura, Kohtaro Gotoh | 2002-12-10 |
| 6115803 | Parallel computer which verifies direct data transmission between local memories with a send complete flag | Kenichi Hayashi, Takeshi Horie, Osamu Shiraki | 2000-09-05 |
| 5892979 | Queue control apparatus including memory to save data received when capacity of queue is less than a predetermined threshold | Osamu Shiraki, Takeshi Horie, Toshiyuki Shimizu, Hiroaki Ishihata | 1999-04-06 |
| 5818755 | Storage apparatus having a nonvolatile storage device capable of retaining data after an incomplete write operation and method of accessing same | Toshiyuki Shimizu | 1998-10-06 |
| 5742843 | Control system for access between processing elements in a parallel computer | Osamu Shiraki, Takeshi Horie, Toshiyuki Shimizu, Hiroaki Ishihata | 1998-04-21 |
| 5604913 | Vector processor having a mask register used for performing nested conditional instructions | Takeshi Horie | 1997-02-18 |