Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7995407 | Semiconductor memory device and control method thereof | — | 2011-08-09 |
| 7457182 | Semiconductor memory including self-timing circuit | Toshiyuki Uetake | 2008-11-25 |
| 7447058 | Write margin of SRAM cells improved by controlling power supply voltages to the inverters via corresponding bit lines | Koji Shimosako | 2008-11-04 |
| 7421364 | Integrated circuit device having a test circuit to measure AC characteristics of internal memory macro | — | 2008-09-02 |
| 7411813 | Semiconductor device | — | 2008-08-12 |
| 7327599 | Semiconductor memory device | — | 2008-02-05 |
| 6870777 | Semiconductor memory device having self-timing circuit | — | 2005-03-22 |
| 6809404 | Semiconductor device | — | 2004-10-26 |
| 6501694 | Precharge circuit with small width | — | 2002-12-31 |
| 6239647 | Decoder circuit and decoding method of the same | Takako Kagiwata, Toshiyuki Uetake | 2001-05-29 |
| 6081444 | Static memory adopting layout that enables minimization of cell area | Hiroshi Shimizu, Hiroshi Kagiwata | 2000-06-27 |
| 5477178 | Data-hold timing adjustment circuit | — | 1995-12-19 |
| 5301148 | Semiconductor memory device with bipolar-FET sense amp | Yoshinori Okajima | 1994-04-05 |
| 4906868 | Logic circuit using bipolar complementary metal oxide semiconductor gate and semiconductor memory device having the logic circuit | Osamu Nomura | 1990-03-06 |
| 4757474 | Semiconductor memory device having redundancy circuit portion | Isao Fukushi | 1988-07-12 |