Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8503259 | Memory test method and memory test device | Shogo Shibazaki, Hideyuki Negi, Takeshi Nagase, Chikahiro Deguchi, Yutaka Sekino | 2013-08-06 |
| 8143901 | Test apparatus, test method, and integrated circuit | Chikahiro Deguchi, Yutaka Sekino, Shogo Shibazaki, Takeshi Nagase, Hideyuki Negi | 2012-03-27 |
| 7689836 | Encryption device | Takeshi Nagase, Shogo Shibazaki | 2010-03-30 |
| 7076667 | Storage device having secure test process | Shogo Shibazaki | 2006-07-11 |
| 6643730 | CPU controlled memory controlling device for accessing operational information | Yoshiki Okumura, Yoshihiro Takamatsuya, Tomohiro Hayashi, Takeshi Nagase | 2003-11-04 |
| 6449681 | Memory unit and buffer access control circuit for updating an address when consecutively accessing upper and lower buffers | Takeshi Nagase, Yoshiki Okumura, Tomohiro Hayashi, Yoshihiro Takamatsuya | 2002-09-10 |
| 6418501 | Memory card | Yoshiki Okumura, Takeshi Nagase, Tomohiro Hayashi, Yoshihiro Takamatsuya | 2002-07-09 |
| 6339809 | Memory unit and buffer access control circuit for updating an address when consecutively accessing upper and lower buffers | Takeshi Nagase, Yoshiki Okumura, Tomohiro Hayashi, Yoshihiro Takamatsuya | 2002-01-15 |
| 6289411 | Circuit for generating a chip-enable signal for a multiple chip configuration | Yoshiki Okumura, Yoshihiro Takamatsuya, Tomohiro Hayashi, Takeshi Nagase | 2001-09-11 |