Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11534139 | Ultrasonic diagnostic device and ultrasonic diagnostic system | Naoto Adachi, Naoto Yoneda, Mari Kobayashi, Amane Inoue | 2022-12-27 |
| 11452505 | Ultrasonic diagnostic apparatus and ultrasonic diagnostic system | Naoto Adachi, Naoto Yoneda, Amane Inoue | 2022-09-27 |
| 11234730 | Ultrasonic probe control method and computer-readable storage medium holding program | Naoto Adachi, Amane Inoue | 2022-02-01 |
| 11229381 | Semiconductor integrated circuit and respiratory motion testing apparatus | Ryusuke Kurachi, Hiroyuki Tomura, Masato Yoshioka, Amane Inoue | 2022-01-25 |
| 11045097 | Blood pressure meter | Ryusuke Kurachi, Masato Yoshioka, Hiroyuki Tomura, Amane Inoue, Minoru Nakagawara | 2021-06-29 |
| D915604 | Ultrasonic probe | Mari Kobayashi, Kazuyuki Kanazashi | 2021-04-06 |
| D915605 | Ultrasonic probe | Mari Kobayashi, Kazuyuki Kanazashi | 2021-04-06 |
| 6535566 | Demodulating method and receiver apparatus | Ken Yamauchi | 2003-03-18 |
| 6118316 | Semiconductor integrated circuit including plurality of phase-locked loops | Syouji Ohishi | 2000-09-12 |
| 6087869 | Digital PLL circuit | Syouji Ohishi, Koichi Hatta | 2000-07-11 |
| 6078633 | PLL circuit and its automatic adjusting circuit | Shinichi Shiotsu | 2000-06-20 |
| 5859551 | Digital PLL circuit | Syouji Ohishi, Koichi Hatta | 1999-01-12 |
| 5694078 | Semiconductor integrated circuit having regularly arranged transistor basic cells | Katsunobu Nomura, Shinichi Shiotsu, Hojo Masayasu | 1997-12-02 |
| 5666387 | Signal processing device having PLL circuits | Shinichi Shiotsu | 1997-09-09 |
| 5321733 | Counter circuit using Johnson-type counter and applied circuit including the same | Shinichi Shiotsu, Katsunobu Nomura | 1994-06-14 |
| 5270586 | Controllable delay logic circuit for providing variable delay time | Shinji Emori | 1993-12-14 |
| 5218230 | IC package with electric conductor lines in dielectric package body | Yoshiro Morino | 1993-06-08 |
| 5128673 | Signal generator for generating a delayed clock signal | Shinji Emori | 1992-07-07 |
| 5001361 | Master-slave flip-flop circuit | Shinji Emori, Yoshio Watanabe, Isao Shimotsuhama | 1991-03-19 |
| 4933576 | Gate array device having macro cells for forming master and slave cells of master-slave flip-flop circuit | Shinji Emori, Yoshio Watanabe, Isao Shimotsuhama | 1990-06-12 |
| 4928024 | Referenceless ECL logic circuit | Isao Shimotsuhama, Shinji Emori, Yoshio Watanabe | 1990-05-22 |