Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11138505 | Quantization of neural network parameters | Xuan TAN | 2021-10-05 |
| 9509327 | A/D converter and A/D converter calibrating method | Sanroku Tsukamoto | 2016-11-29 |
| 9118451 | Receiver circuit and receiving method | Hirotaka Tamura | 2015-08-25 |
| 8798568 | Signal transmission method, transmission circuit and apparatus | — | 2014-08-05 |
| 8797076 | Duty ratio correction circuit, double-edged device, and method of correcting duty ratio | — | 2014-08-05 |
| 8634454 | Receiver circuit, method of adjusting offset, and transmission/reception system | Hirotaka Tamura | 2014-01-21 |
| 8588359 | Reception circuit, reception method, and signal transfer system | — | 2013-11-19 |
| 8320503 | Receiver | Hirotaka Tamura | 2012-11-27 |
| 8319542 | Integrated circuit including bypass signal path | Hirotaka Tamura | 2012-11-27 |
| 8299948 | Receiving circuit and sampling clock control method | Takayuki Shibasaki, Takuji Yamamoto | 2012-10-30 |
| 8238504 | Clock generation circuit and system | Yasumoto Tomita, Hirotaka Tamura | 2012-08-07 |
| 8031091 | Reception circuit, method of creating AD converter conversion table of reception circuit, and signal transfer system | — | 2011-10-04 |
| 7973691 | Data recovery circuit, data recovery method and data receiving apparatus | Hisakatsu Yamaguchi, Hirotaka Tamura | 2011-07-05 |
| 7936296 | AD converter, data receiver and data reception method | Hisakatsu Yamaguchi | 2011-05-03 |
| 7859300 | Input and output circuit apparatus | — | 2010-12-28 |
| 7598780 | Clock buffer | — | 2009-10-06 |
| 7508892 | Receiver circuit comprising equalizer | Hirotaka Tamura | 2009-03-24 |
| 7283601 | Timing signal generating system and receiving circuit for transmitting signals at high speed with less circuitry | Hirotaka Tamura | 2007-10-16 |
| 6963237 | Output circuit device for clock signal distribution in high-speed signal transmission | Hirotaka Tamura | 2005-11-08 |
| 6812777 | Output circuit device for clock signal distribution in high-speed signal transmission | Hirotaka Tamura | 2004-11-02 |