Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9141465 | Reception circuit, information processing apparatus, and control method | — | 2015-09-22 |
| 8619930 | Synchronization circuit and synchronization method | — | 2013-12-31 |
| 8539306 | Data processing circuit and data processing method | — | 2013-09-17 |
| 7882279 | Bidirectional control circuit | — | 2011-02-01 |
| 7257666 | Method of writing, erasing, and controlling memory for memory device | Shinpei Komatsu, Yumi Ishii, Tomohiro Hayashi, Shogo Shibazaki, Hiroyuki Itoh | 2007-08-14 |
| 6766409 | Method of writing, erasing, and controlling memory for memory device | Shinpei Komatsu, Yumi Ishii, Tomohiro Hayashi, Shogo Shibazaki, Hiroyuki Itoh | 2004-07-20 |
| 6584579 | Method of writing, erasing, and controlling memory for memory device | Shinpei Komatsu, Yumi Ishii, Tomohiro Hayashi, Shogo Shibazaki, Hiroyuki Itoh | 2003-06-24 |
| 6161163 | Method of writing, erasing, and controlling memory for memory device | Shinpei Komatsu, Yumi Ishii, Tomohiro Hayashi, Shogo Shibazaki, Hiroyuki Itoh | 2000-12-12 |
| 6125424 | Method of writing, erasing, and controlling memory and memory device having erasing and moving components | Shinpei Komatsu, Yumi Ishii, Tomohiro Hayashi, Shogo Shibazaki, Hiroyuki Itoh | 2000-09-26 |
| 5983312 | Simultaneously writing to and erasing two commonly numbered sectors | Shinpei Komatsu, Yumi Ishii, Tomohiro Hayashi, Shogo Shibazaki, Hiroyuki Itoh | 1999-11-09 |
| 5802551 | Method and apparatus for controlling the writing and erasing of information in a memory device | Shinpei Komatsu, Yumi Ishii, Tomohiro Hayashi, Shogo Shibazaki, Hiroyuki Itoh | 1998-09-01 |