Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6217375 | Wiring harness arranging construction | Satoshi Nagai, Tetuya Funaki, Yasuhiro Ando, Shinya Miyamoto | 2001-04-17 |
| 6107570 | Wiring harness arranging construction | Tetsuya Takimoto, Yasuhiro Ando, Tetuya Funaki, Shinichi Suehiro | 2000-08-22 |
| 6079764 | Wiring harness arranging construction | Tetsuya Takimoto, Yasuhiro Ando, Tetuya Funaki, Shinichi Suehiro | 2000-06-27 |
| 5994645 | Wiring harness arranging construction | Tetsuya Takimoto, Yasuhiro Ando, Tetuya Funaki, Shinichi Suehiro | 1999-11-30 |
| 5957702 | Wiring harness arranging construction | Satoshi Nagai, Tetuya Funaki, Yasuhiro Ando, Shinya Miyamoto | 1999-09-28 |
| D397092 | Integrated circuit package | Yoshiaki Sano, Takashi Yoshida, Takahisa Kawai | 1998-08-18 |
| 5358900 | Semiconductor device having overlapping conductor layers and method of producing the semiconductor device | — | 1994-10-25 |
| 5276340 | Semiconductor integrated circuit having a reduced side gate effect | Teruo Yokoyama, Tomonori Ishikawa, Takeshi Igarashi | 1994-01-04 |
| 5252843 | Semiconductor device having overlapping conductor layers | — | 1993-10-12 |
| 4615102 | Method of producing enhancement mode and depletion mode FETs | Takashi Mimura | 1986-10-07 |