Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6535902 | Multiplier circuit for reducing the number of necessary elements without sacrificing high speed capability | — | 2003-03-18 |
| 6240438 | Multiplier circuit for reducing the number of necessary elements without sacrificing high speed capability | — | 2001-05-29 |
| 5920498 | Compression circuit of an adder circuit | — | 1999-07-06 |
| 5465226 | High speed digital parallel multiplier | — | 1995-11-07 |
| 5434810 | Binary operator using block select look ahead system which serves as parallel adder/subtracter able to greatly reduce the number of elements of circuit with out sacrifice to high speed of computation | Hajime Kubosawa | 1995-07-18 |
| 5047976 | Logic circuit having carry select adders | Hajime Kubosawa | 1991-09-10 |
| 5025409 | Carry propagation circuit of parallel-type full adder | — | 1991-06-18 |
| 4668972 | Masterslice semiconductor device | Shinji Sato | 1987-05-26 |