Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9069762 | Equivalence classes over parameter state space | Yinfang Lin, Jayanta Bhadra | 2015-06-30 |
| 9043737 | Integrated circuit design verification through forced clock glitches | Jayanta Bahadra, Xiao Sun | 2015-05-26 |
| 9002694 | Verification of design derived from power intent | Jayanta Bhadra, Scott R. Little | 2015-04-07 |
| 8584063 | Assertion-based design partitioning | Jayanta Bhadra, Ross L. Patterson | 2013-11-12 |
| 8555226 | Automatic verification of dependency | Jayanta Bhadra, Ashish Goel | 2013-10-08 |
| 7954075 | Vector sequence simplification for circuit verification | — | 2011-05-31 |