Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9594860 | Analog mixed signal model equivalence checking | Himyanshu Anand | 2017-03-14 |
| 9329229 | Integrated circuit with degradation monitoring | Puneet Sharma | 2016-05-03 |
| 9287006 | System and method for testing address-swap faults in multiport memories | Rajesh Raina | 2016-03-15 |
| 9135195 | Prediction of electronic component behavior in bus-based systems | Aseem Gupta | 2015-09-15 |
| 9069042 | Efficient apparatus and method for testing digital shadow logic around non-logic design structures | Rajesh Raina, Darrell L. Carder | 2015-06-30 |
| 8898614 | Integrated circuit device with reduced leakage and method therefor | Puneet Sharma, Scott Warrick | 2014-11-25 |
| 8127258 | Data processing device design tool and methods | Aseem Gupta, Kamal S. Khouri, Puneet Sharma | 2012-02-28 |
| 8050904 | System and method for circuit symbolic timing analysis of circuit designs | Jayanta Bhadra, Ping Gao, Timothy David McDougall | 2011-11-01 |
| 7650579 | Model correspondence method and device | Himyanshu Anand, M. Alper Sen, Jayanta Bhadra | 2010-01-19 |
| 7647573 | Method and device for testing delay paths of an integrated circuit | Jing Zeng, Benjamin N. Lee | 2010-01-12 |
| 7360183 | Design analysis tool and method for deriving correspondence between storage elements of two memory models | Jayanta Bhadra, Himyanshu Anand | 2008-04-15 |
| 7003743 | Method and system of data processor design by sensitizing logical difference | Andreas Veneris | 2006-02-21 |
| 6952812 | Design analysis tool for path extraction and false path identification and method thereof | Jing Zeng, Jayanta Bhadra | 2005-10-04 |
| 6651227 | Method for generating transition delay fault test patterns | Juhong Zhu | 2003-11-18 |
| 6378112 | Verification of design blocks and method of equivalence checking of multiple design views | Andrew K. Martin, Narayanan Krishamurthy, Li-Chung Wang | 2002-04-23 |