Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7902021 | Method for separately optimizing spacer width for two or more transistor classes using a recess spacer integration | — | 2011-03-08 |
| 7820539 | Method for separately optimizing spacer width for two transistor groups using a recess spacer etch (RSE) integration | — | 2010-10-26 |
| 7563700 | Method for improving self-aligned silicide extendibility with spacer recess using an aggregated spacer recess etch (ASRE) integration | Mark D. Hall, Raghaw S. Rai, Jesse Yanez | 2009-07-21 |