Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12087716 | Techniques for positioning bond pads of microelectronic devices and related microelectronic devices, methods, and systems | Ken Ota, Saaya Izumi | 2024-09-10 |
| 11081467 | Apparatuses and methods for arranging through-silicon vias and pads in a semiconductor device | — | 2021-08-03 |
| 9337139 | Semiconductor device having compensation capacitor to stabilize power supply voltage | Hisayuki Nagamine | 2016-05-10 |
| 8860187 | Semiconductor device | Hisayuki Nagamine | 2014-10-14 |
| 8704339 | Semiconductor device | Hisayuki Nagamine | 2014-04-22 |
| 7856610 | Method and apparatus for semiconductor integrated circuit | — | 2010-12-21 |
| 7761835 | Semiconductor device design method, semiconductor device design system, and computer program for extracting parasitic parameters | Hisayuki Nagamine | 2010-07-20 |
| 7730431 | Design method, design apparatus, and computer program for semiconductor integrated circuit | — | 2010-06-01 |
| 7698675 | Method and design system for semiconductor integrated circuit with a reduced placement area | — | 2010-04-13 |
| 6834004 | Semiconductor integrated circuit having logic circuit comprising transistors with lower threshold voltage values and improved pattern layout | Susumu Takano, Hiroyuki Takahashi, Minoru Nizaka | 2004-12-21 |
| 6831484 | Semiconductor integrated circuit having logic circuit comprising transistors with lower threshold voltage values and improved pattern layout | Susumu Takano, Hiroyuki Takahashi, Minoru Nizaka | 2004-12-14 |
| 6545892 | Semiconductor integrated circuit having logic circuit comprising transistors with lower threshold voltage values and improved pattern layout | Susumu Takano, Hiroyuki Takahashi, Minoru Nizaka | 2003-04-08 |
| 6072731 | Semiconductor memory circuit | — | 2000-06-06 |