Issued Patents All Time
Showing 26–50 of 70 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8107315 | Double data rate memory device having data selection circuit and data paths | — | 2012-01-31 |
| 8106692 | Method for tracking delay locked loop clock | — | 2012-01-31 |
| 8081520 | Over erase correction method of flash memory apparatus | — | 2011-12-20 |
| 8045374 | Erase verification method of flash memory by selectively assigning deselected sectors | — | 2011-10-25 |
| 8031550 | Voltage regulator circuit for a memory circuit | — | 2011-10-04 |
| 7929366 | Temperature detector in an integrated circuit | — | 2011-04-19 |
| 7924610 | Method for conducting over-erase correction | Chung-Shan Kuo, Tzeng-Ju Hsue, Ching Tsann Leu | 2011-04-12 |
| 7847617 | Charge pump and method for operating the same | — | 2010-12-07 |
| 7804326 | Voltage level shifter | — | 2010-09-28 |
| 7705631 | Level shifter circuit | — | 2010-04-27 |
| 7643352 | Method for erasing flash memory | — | 2010-01-05 |
| 7630267 | Temperature detector in an integrated circuit | — | 2009-12-08 |
| 7606952 | Method for operating serial flash memory | — | 2009-10-20 |
| 7547941 | NAND non-volatile two-bit memory and fabrication method | — | 2009-06-16 |
| 7525849 | Flash memory with sequential programming | — | 2009-04-28 |
| 7466611 | Selection method of bit line redundancy repair and apparatus performing the same | — | 2008-12-16 |
| 7443230 | Charge pump circuit | Chung-Shan Kuo, Yang-Chieh Lin | 2008-10-28 |
| 7403427 | Method and apparatus for reducing stress in word line driver transistors during erasure | — | 2008-07-22 |
| 7391651 | Method for programming NAND flash memory device and page buffer performing the same | — | 2008-06-24 |
| 7366040 | Method of reducing settling time in flash memories and improved flash memory | — | 2008-04-29 |
| 7359248 | Methods for programming and reading NAND flash memory device and page buffer performing the same | Jo-Yu Wang, Fu-An Wu | 2008-04-15 |
| 7336543 | Non-volatile memory device with page buffer having dual registers and methods using the same | Jo-Yu Wang | 2008-02-26 |
| 7336532 | Method for reading NAND memory device and memory cell array thereof | — | 2008-02-26 |
| 7305513 | Circuit for preventing nonvolatile memory from over-erase | — | 2007-12-04 |
| 7277329 | Erase method to reduce erase time and to prevent over-erase | Chung-Shan Kuo | 2007-10-02 |