JP

John Pierce

EI Eaglestone Partners I: 6 patents #2 of 3Top 70%
CS Cadence Design Systems: 5 patents #303 of 2,263Top 15%
RI Research Triangle Institute: 1 patents #166 of 344Top 50%
Overall (All Time): #340,249 of 4,157,543Top 9%
14
Patents All Time

Issued Patents All Time

Showing 1–14 of 14 patents

Patent #TitleCo-InventorsDate
12135966 Configuration-driven applications Akshay Singh, Scott Knowles, Bryan Chance, Zhuofan Zhang, John Sternberg +1 more 2024-11-05
11842187 Configuration-driven applications Akshay Singh, Scott Knowles, Bryan Chance, Zhuofan Zhang, John Sternberg +1 more 2023-12-12
9619597 System, method, and computer program product for electronic design configuration space determination and verification Adam D. Sherer, Daniel A. Cohen 2017-04-11
9477800 System, method, and computer program product for automatically selecting a constraint solver algorithm in a design verification environment Daniel A. Cohen, Nir Weiss 2016-10-25
9373077 System and method for identifying constraint solver calls Daniel A. Cohen, Petr Spacek, Prasanna Rao 2016-06-21
9202004 System, method, and computer program product for ensuring that each simulation in a regression is running a unique configuration Daniel A. Cohen, Nir Weiss 2015-12-01
8904321 System and method for automatically generating coverage constructs and constraint solver distributions Daniel A. Cohen, Petr Spacek 2014-12-02
7036218 Method for producing a wafer interposer for use in a wafer interposer assembly 2006-05-02
6933617 Wafer interposer assembly 2005-08-23
6673653 Wafer-interposer using a ceramic substrate 2004-01-06
6529022 Wafer testing interposer for a conventional package 2003-03-04
6524885 Method, apparatus and system for building an interposer onto a semiconductor wafer using laser techniques 2003-02-25
6440771 Method for constructing a wafer interposer by using conductive columns 2002-08-27
4837447 Rasterization system for converting polygonal pattern data into a bit-map Nick Kanopoulos 1989-06-06