Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12393738 | Enhanced circuity security through hidden state transitions | Kyle Joseph Juretus | 2025-08-19 |
| 12379767 | On-chip voltage assignment through particle swarm optimization | Divya Pathak | 2025-08-05 |
| 11971987 | Reducing logic locking key leakage through the scan chain | Kyle Joseph Juretus | 2024-04-30 |
| 11641200 | Charge recycling from idle circuits for improved energy efficiency of multi-voltage systems | Md Shazzad Hossain | 2023-05-02 |
| 11540120 | Physical layer key based interleaving for secure wireless communication | Kapil R. Dandekar, James J. Chacko, Kyle Joseph Juretus, Marko Jacovic, Cem Sahin +1 more | 2022-12-27 |
| 11444210 | On-chip power supply noise suppression through hyperabrupt junction varactors | Divya Pathak | 2022-09-13 |
| 11435802 | Work load scheduling for multi core systems with under-provisioned power delivery | Divya Pathak, Houman Homayoun | 2022-09-06 |
| 11282414 | Reduced overhead gate level logic encryption | Kyle Joseph Juretus | 2022-03-22 |
| 11270031 | Securing analog mixed-signal integrated circuits through shared dependencies | Vaibhav Venugopal Rao, Kyle Joseph Juretus | 2022-03-08 |
| 11177902 | Physical gate based preamble obfuscation for securing wireless communication | James J. Chacko, Kapil R. Dandekar, Marko Jacovic, Kyle Joseph Juretus, Nagarajan Kandasamy +1 more | 2021-11-16 |
| 11157674 | Transistor sizing for parameter obfuscation of analog circuits | Vaibhav Venugopal Rao | 2021-10-26 |
| 10923442 | Protecting analog circuits with parameter biasing obfuscation | Vaibhav Venugopal Rao, Kyle Joseph Juretus | 2021-02-16 |
| 9912325 | Power supply voltage detection and power delivery circuit | Divya Pathak | 2018-03-06 |