Issued Patents All Time
Showing 1–25 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8799706 | Method and system of exchanging information between processors | David J. Garcia, Thomas A. Heynemann, James S. Klecka, Jeffrey A. Sprouse | 2014-08-05 |
| 8103861 | Method and system for presenting an interrupt request to processors executing in lock step | James S. Klecka, Mihai Damian, Peter A. Reynolds, Dale E. Southgate | 2012-01-24 |
| 7933966 | Method and system of copying a memory area between processor elements for lock-step execution | Thomas J. Kondo, Robert L. Jardine, James S. Klecka, David J. Garcia, James R. Smullen +1 more | 2011-04-26 |
| 7730350 | Method and system of determining the execution point of programs executed in lock step | Dale E. Southgate, Mihai Damian, Peter A. Reynolds, James S. Klecka | 2010-06-01 |
| 7590885 | Method and system of copying memory from a source processor to a target processor by duplicating memory writes | Thomas J. Kondo, Robert L. Jardine, David J. Garcia, James S. Klecka, James R. Smullen +2 more | 2009-09-15 |
| 7549082 | Method and system of bringing processors to the same computational point | Dale E. Southgate, Mihai Damian, Peter A. Reynolds, James S. Klecka | 2009-06-16 |
| 7516358 | Tuning core voltages of processors | Juerg Haefliger, James S. Klecka | 2009-04-07 |
| 7434098 | Method and system of determining whether a user program has made a system level call | David Bernick, David J. Garcia, Robert L. Jardine, Pankaj Mehra, James R. Smullen | 2008-10-07 |
| 7426656 | Method and system executing user programs on non-deterministic processors | David Bernick, David J. Garcia, Robert L. Jardine, James S. Klecka, Pankaj Mehra +1 more | 2008-09-16 |
| 7426614 | Method and system of executing duplicate copies of a program in lock step | Mihai Damian, James S. Klecka, Peter A. Reynolds, Dale E. Southgate | 2008-09-16 |
| 6950428 | System and method for configuring adaptive sets of links between routers in a system area network (SAN) | Robert W. Horst, William J. Watson, David A. Brown, David J. Garcia, William P. Bunton +1 more | 2005-09-27 |
| 6393582 | Error self-checking and recovery using lock-step processor pair architecture | James S. Klecka, Robert L. Jardine | 2002-05-21 |
| 6233702 | Self-checked, lock step processor pairs | Robert W. Horst, David J. Garcia, William P. Bunton, Daniel L. Fowler, Curtis Willard Jones, Jr. +3 more | 2001-05-15 |
| 5751932 | Fail-fast, fail-functional, fault-tolerant multiprocessor system | Robert W. Horst, William E. Baker, Randall G. Banton, John M. Brown, William P. Bunton +21 more | 1998-05-12 |
| 5689689 | Clock circuits for synchronized processor systems having clock generator circuit with a voltage control oscillator producing a clock signal synchronous with a master clock signal | Steven C. Meyers, John M. Brown, James S. Klecka | 1997-11-18 |
| 5675579 | Method for verifying responses to messages using a barrier message | William J. Watson, William E. Baker, William P. Bunton, David J. Garcia, Robert W. Horst +3 more | 1997-10-07 |
| 5347559 | Apparatus and method of data transfer between systems using different clocks | Thomas B. Hawkins, Thomas D. Bissett | 1994-09-13 |
| 5339408 | Method and apparatus for reducing checking costs in fault tolerant processors | Thomas D. Bissett, Glenn Dearth, Paul Paternoster | 1994-08-16 |
| 5291494 | Method of handling errors in software | Thomas D. Bissett, James Melvin | 1994-03-01 |
| 5255367 | Fault tolerant, synchronized twin computer system with error checking of I/O communication | Thomas D. Bissett, Dennis Mazur, John Munzer | 1993-10-19 |
| 5251227 | Targeted resets in a data processor including a trace memory to store transactions | Thomas D. Bissett, John Munzer, David E. Kovalcin, Mitchell Norcross | 1993-10-05 |
| 5249187 | Dual rail processors with error checking on I/O reads | Thomas D. Bissett | 1993-09-28 |
| 5185877 | Protocol for transfer of DMA data | Thomas D. Bissett, Ajai Thirumalai, Jay Amirmokri | 1993-02-09 |
| 5153881 | Method of handling errors in software | Thomas D. Bissett, James Melvin | 1992-10-06 |
| 5099485 | Fault tolerant computer systems with fault isolation and repair | Thomas D. Bissett, Dennis Mazur, John Munzer, Frank Bernaby, Jay H. Bhatia | 1992-03-24 |