Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8311781 | Selectively reducing the number of cell evaluations in a hardware simulation | Du Nguyen, Joseph Rodriguez | 2012-11-13 |
| 7555417 | Selectively reducing the number of cell evaluations in a hardware simulation | Du Nguyen, Joseph Rodriguez | 2009-06-30 |
| 7181706 | Selectively reducing the number of cell evaluations in a hardware simulation | Du Nguyen, Joseph Rodriguez | 2007-02-20 |
| 6961689 | Scheduling non-integral simulation time for mixed-signal simulation | — | 2005-11-01 |
| 5157778 | Method and apparatus for circuit simulation using parallel processors including memory arrangements and matrix decomposition synchronization | Gabriel Bischoff | 1992-10-20 |