Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11510293 | Dali line-failure-based driver dimming mode detection via load power measurement | James R. Burt, Vaske Mikani | 2022-11-22 |
| 10602590 | Isolation of digital signals in a lighting control transceiver | Dalibor Zulim, Nathaniel Christopher Herwig | 2020-03-24 |
| 10312730 | Emergency lighting system and method for automatic heating power equalization | Jon P. Baker, Long Wang | 2019-06-04 |
| 9999108 | Emergency lighting driver with programmable output power | David Crenshaw, ABHISHEK CHANDRASHEKHAR SABNIS, Shawn Croley, Brian Inman, TAWATOS PHADUNGSOONDARARAK +1 more | 2018-06-12 |
| 9930757 | Digital communication interface circuit for line-pair with duty cycle imbalance compensation | — | 2018-03-27 |
| 9521730 | Digital communication interface circuit for line-pair with duty cycle imbalance compensation | — | 2016-12-13 |
| 9439270 | Digital communication receiver interface circuit for line-pair with duty cycle imbalance compensation | — | 2016-09-06 |
| 9131549 | Digital communication interface circuit for line-pair with individually adjustable transition edges | — | 2015-09-08 |
| 8397034 | Multi-port arbitration system and method | — | 2013-03-12 |
| 8239658 | Internally derived address generation system and method for burst loading of a synchronous memory | — | 2012-08-07 |
| 7813213 | Pulsed arbitration system | — | 2010-10-12 |
| 7796464 | Synchronous memory with a shadow-cycle counter | — | 2010-09-14 |
| 7516280 | Pulsed arbitration system and method | — | 2009-04-07 |
| 7173469 | Clocking system and method for a memory | — | 2007-02-06 |
| 6789180 | Method and apparatus for mask and/or counter address registers readback on the address bus in synchronous single and multi-port memories | — | 2004-09-07 |
| 6782467 | Method and apparatus for fast limited core area access and cross-port word size multiplication in synchronous multiport memories | — | 2004-08-24 |
| 6567884 | Endian-controlled counter for synchronous ports with bus matching | — | 2003-05-20 |
| 6510483 | Circuit, architecture and method for reading an address counter and/or matching a bus width through one or more synchronous ports | James D. Allan, Emad Hamadeh, Eric Gross, Vijay Srinivasaraghavan, Robert Manning | 2003-01-21 |
| 6157582 | Dynamic pull-up suppressor for column redundancy write schemes with redundant data lines | — | 2000-12-05 |
| 6122221 | Scheme for increasing enable access speed in a memory device | — | 2000-09-19 |
| 6081475 | Write control apparatus for memory devices | — | 2000-06-27 |
| 5889728 | Write control method for memory devices | — | 1999-03-30 |
| 5825715 | Method and apparatus for preventing write operations in a memory device | — | 1998-10-20 |