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Anti-fuse latch self-test circuit and method |
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2010-12-28 |
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Charge pump circuit and method for phase locked loop |
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2010-08-17 |
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Well bias architecture for integrated circuit device |
King Kwan, Xiaolin Ouyang |
2009-10-06 |
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Device and method for sensing programming status of non-volatile memory elements |
Tomasz Cewe |
2008-09-16 |
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Anti-fuse latch circuit and method including self-test |
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2008-03-04 |
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Method and apparatus for converging a control loop |
King Hong Kwan |
2004-09-28 |
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Robust clock circuit architecture |
John J. Wunner |
2004-01-06 |
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Multi-modulus counter in modulated frequency synthesis |
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2003-05-06 |
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Loadable divide-by-N with fixed duty cycle |
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2002-12-31 |
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Clock generator with programmable two-tone modulation for EMI reduction |
Eric N. Mann, Monte Mar |
2002-04-16 |
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Clock circuit for generating a delay |
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2001-08-07 |
| 6175259 |
Clock generator with programmable two-tone modulation for EMI reduction |
Eric N. Mann, Monte Mar |
2001-01-16 |
| 5886582 |
Enabling clock signals with a phase locked loop (PLL) lock detect circuit |
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1999-03-23 |
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Latching inputs and enabling outputs on bidirectional pins with a phase locked loop (PLL) lock detect circuit |
J. Kenneth Fox, Eric N. Mann, James Paul Myers, Timothy Wright |
1998-06-09 |