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Circuits, integrated circuits, and methods for interleaved parity computation |
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Circuits, integrated circuits, and methods for interleaved parity computation |
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2014-08-12 |
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Array substrate and display apparatus using the same |
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Low power synchronous memory command address scheme |
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Golf club face assistance device |
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High speed FIFO synchronous programmable full and empty flag generation |
Johnie Au, Parinda Mekara |
2006-10-03 |
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High speed asynchronous and programmable state machine for generating almost full synchronous flags in a synchronous FIFO |
Johnie Au, Parinda Mekara |
2005-11-29 |
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High speed FIFO synchronous programmable full and empty flag generation |
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2003-02-25 |
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High speed asynchronous and programmable state machine for generating almost empty synchronous flags in a synchronous FIFO |
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2002-09-03 |
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Self-bootstrapping word-line driver circuit and method |
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Redundancy programming circuit and system for semiconductor memory |
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