Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6012135 | Computer having multiple address ports, each having logical address translation with base and limit memory management | William T. Moore | 2000-01-04 |
| 5717895 | Associative scalar data cache with write-through capabilities for a vector processor | William T. Moore | 1998-02-10 |
| 5623685 | Vector register validity indication to handle out-of-order element arrival for a vector computer with variable memory latency | William T. Moore | 1997-04-22 |
| 5390300 | Real time I/O operation in a vector processing computer system by running designated processors in privileged mode and bypass the operating system | Richard D. Pribnow, Galen C. Flunker, Alan J. Schiffleger | 1995-02-14 |
| 5247637 | Method and apparatus for sharing memory in a multiprocessor system | Alan J. Schiffleger, Ram K. Gupta | 1993-09-21 |