Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6813599 | Efficient memory structure simulation for sequential circuit design verification | Thomas L. Court, Abdulla M. Bataineh | 2004-11-02 |
| 5349677 | Apparatus for calculating delay when executing vector tailgating instructions and using delay to facilitate simultaneous reading of operands from and writing of results to same vector register | Seymour R. Cray, James R. Bedell, William T. Moore | 1994-09-20 |