SP

Santosh Patel

CS Conexant Systems: 1 patents #311 of 657Top 50%
Overall (All Time): #3,115,581 of 4,157,543Top 75%
1
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8779816 Low area all digital delay-locked loop insensitive to reference clock duty cycle and jitter Pradeep Anantula 2014-07-15