VT

Vikas Trivedi

CI Ciena: 2 patents #497 of 1,406Top 40%
Overall (All Time): #1,932,636 of 4,157,543Top 50%
2
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10237088 Systems and methods for avoiding inadvertent loops in a layer 2 switched network Rajneesh Mishra, Prashant Vashisht 2019-03-19
10015066 Propagation of frame loss information by receiver to sender in an ethernet network Rajneesh Mishra, Prashant Vashisht, Jayant Kumar Bhardwaj 2018-07-03