JW

Junxian Weng

CI Ciena: 2 patents #497 of 1,406Top 40%
Overall (All Time): #1,423,668 of 4,157,543Top 35%
3
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11502695 High bandwidth under-sampled successive approximation register analog to digital converter with nonlinearity minimization Christopher Kurowski, Sadok Aouini, Naim Ben-Hamida 2022-11-15
10965300 High bandwidth under-sampled successive approximation register analog to digital converter with nonlinearity minimization Christopher Kurowski, Sadok Aouini, Naim Ben-Hamida 2021-03-30
6774721 High speed logic circuits Petre Popescu, David Dobson, Guy Fortier 2004-08-10