Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12068024 | Address dependent wordline timing in asynchronous static random access memory | Jay A. Chesavage, Robert Francis Wiser | 2024-08-20 |
| 11971448 | Process for scan chain in a memory | Robert Francis Wiser, Shakti Singh | 2024-04-30 |
| 11935587 | Dynamic adjustment of wordline timing in static random access memory | Robert Francis Wiser | 2024-03-19 |
| 11862282 | One transistor memory bitcell with arithmetic capability | Robert Francis Wiser | 2024-01-02 |
| 11693056 | Scan chain for memory with reduced power consumption | Robert Francis Wiser, Shakti Singh | 2023-07-04 |