BR

Bradley R. Roetcisoender

CA Cascade Design Automation: 1 patents #1 of 17Top 6%
SY Synopsys: 1 patents #1,143 of 2,302Top 50%
📍 Kirkland, WA: #1,774 of 3,517 inventorsTop 55%
🗺 Washington: #35,300 of 76,902 inventorsTop 50%
Overall (All Time): #2,151,522 of 4,157,543Top 55%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
7451412 Speeding up timing analysis by reusing delays computed for isomorphic subcircuits Larry G. Jones, Feng Li, Mohan Govindaraj, Michael G. Weaver 2008-11-11
5654898 Timing-driven integrated circuit layout through device sizing Yongtao You, Richard K. McGehee 1997-08-05