JS

Jose V. Siles

Caltech: 3 patents #909 of 4,321Top 25%
🗺 California: #149,087 of 386,348 inventorsTop 40%
Overall (All Time): #1,484,010 of 4,157,543Top 40%
3
Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
10100858 Wafer-to-wafer alignment method Cecile D. Jung-Kubiak, Theodore Reck, Bertrand Thomas, Robert H. Lin, Alejandro Peralta +6 more 2018-10-16
9791321 340 GHz multipixel transceiver Goutam Chattopadhyay, Ken B. Cooper, Emmanuel Decrossas, John J. Gill, Cecile D. Jung-Kubiak +5 more 2017-10-17
9512863 Silicon alignment pins: an easy way to realize a wafer-to-wafer alignment Cecile D. Jung-Kubiak, Theodore Reck, Bertrand Thomas, Robert H. Lin, Alejandro Peralta +6 more 2016-12-06