Ywh-Pyng Harn

CS Cadence Design Systems: 3 patents #541 of 2,263Top 25%

📍 Milpitas, CA: #1,297 of 3,192 inventorsTop 45%

🗺 California: #149,087 of 386,348 inventorsTop 40%

Overall (All Time): #1,587,655 of 4,157,543Top 40%

Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #	Title	Co-Inventors	Date
7225116	Method for eliminating routing congestion in an IC layout	—	2007-05-29
7137093	Post-placement timing optimization of IC layout	—	2006-11-14
6668365	Quadratic programming method for eliminating cell overlap and routing congestion in an IC layout	—	2003-12-23