YL

Yufeng Luo

CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
FW Federal-Mogul Worldwide: 1 patents #180 of 317Top 60%
📍 San Jose, CA: #14,517 of 32,062 inventorsTop 50%
🗺 California: #149,087 of 386,348 inventorsTop 40%
Overall (All Time): #1,410,681 of 4,157,543Top 35%
3
Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
11276677 Concurrent optimization of 3D-IC with asymmetrical routing layers Liqun Deng, Pinhong Chen, Richard Chou, Chin-Chih Chang, Miao Liu 2022-03-15
7191417 Method and apparatus for optimization of digital integrated circuits using detection of bottlenecks Prasanna Venkat Srinivas, Shankar Krishnamoorthy 2007-03-13
7175752 Method and apparatus for electrochemical machining 2007-02-13