Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9423812 | Current mode boost converter using slope compensation | Roy Shoshani | 2016-08-23 |
| 9288065 | Techniques for protecting digital multimedia interfaces | Genady Veytsman, Evgeny Rogachov, Gilad KIRSHENBOIM | 2016-03-15 |
| 9197023 | Apparatus for enabling simultaneous content streaming and power charging of handheld devices | Amir Bar-Niv, Ziv Kabiry | 2015-11-24 |
| 8949481 | Techniques for achieving complete interoperability between different types of multimedia display interfaces | Amir Bar-Niv, Ziv Kabiry | 2015-02-03 |
| 8886852 | Techniques for achieving complete interoperability between different types of data and multimedia interfaces in handheld devices | Amir Bar-Niv, Ziv Kabiry | 2014-11-11 |
| 8878590 | Techniques for switching between AC-coupled connectivity and DC-coupled connectivity | — | 2014-11-04 |
| 8837573 | Apparatus and method thereof for compensating for gain changes of N-PAM modulate signals | Eran Doron, Baruch Bublil, Idan Versano | 2014-09-16 |
| 8804809 | Techniques for setting feedback coefficients of a PAM-N decision feedback equalizer | Dan Raphaeli | 2014-08-12 |
| 8594262 | Apparatus and method thereof for clock and data recovery of N-PAM encoded signals using a conventional 2-PAM CDR circuit | Genady Veytsman | 2013-11-26 |
| 8576903 | Techniques for adaptively adjusting decision levels of a PAM-N decision feedback equalizer | Dan Raphaeli | 2013-11-05 |
| 8222874 | Current mode boost converter using slope compensation | Roy Shoshani | 2012-07-17 |
| 6628173 | Data and clock extractor with improved linearity | Avraham Cohen | 2003-09-30 |
| 6430719 | General port capable of implementing the JTAG protocol | Arye Ziklik, Cuong Trinh | 2002-08-06 |
| 6243842 | Method and apparatus for operating on a memory unit via a JTAG port | Yoram Cedar, Ilan Wienner | 2001-06-05 |
| 5719818 | Row decoder having triple transistor word line drivers | Asaf Ben Tovim | 1998-02-17 |
| 5696730 | First read cycle circuit for semiconductor memory | Boaz Eitan | 1997-12-09 |
| 5682353 | Self adjusting sense amplifier clock delay circuit | Boaz Eitan, Larry W. Petersen | 1997-10-28 |
| 5511032 | Source pre-charge system in a memory array | William Kammerer, Baruch R. Friedlander | 1996-04-23 |