WG

Wilsin Gosti

CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
IN Intel: 1 patents #18,218 of 30,777Top 60%
📍 Merced, CA: #65 of 257 inventorsTop 30%
🗺 California: #149,087 of 386,348 inventorsTop 40%
Overall (All Time): #1,539,852 of 4,157,543Top 40%
3
Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
8386987 Method and system for implementing and analyzing power switch configurations 2013-02-26
7551985 Method and apparatus for power consumption optimization for integrated circuits Pinhong Chen 2009-06-23
6308303 Wire tapering under reliability constraints Sriram Mysore 2001-10-23