SL

Stefano Lorenzini

CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
IN Intel: 1 patents #18,218 of 30,777Top 60%
📍 San Giuliano Terme, IT: #9 of 34 inventorsTop 30%
Overall (All Time): #1,804,853 of 4,157,543Top 45%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
11630938 Failure mode analysis for circuit design Antonino Armato 2023-04-18
10248492 Method of executing programs in an electronic system for applications with functional safety comprising a plurality of processors, corresponding system and computer program product Riccardo Mariani, Michele Borgatti 2019-04-02