PC

Praveen Kumar Chhabra

CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
📍 Noida, IN: #227 of 795 inventorsTop 30%
Overall (All Time): #1,880,480 of 4,157,543Top 50%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
11036906 Method and apparatus to accelerate verification signoff by selective re-use of integrated coverage models Devraj Goyal, Amit Kumar Tiwari, Manisha Singla 2021-06-15
10031991 System, method, and computer program product for testbench coverage Hemant Gupta, Sharad Gaur, Matthew Aaron Graham, John Laurence Rose, Anupam Singal 2018-07-24