PB

Pranav Bhushan

CS Cadence Design Systems: 3 patents #541 of 2,263Top 25%
📍 San Jose, CA: #14,517 of 32,062 inventorsTop 50%
🗺 California: #149,087 of 386,348 inventorsTop 40%
Overall (All Time): #1,527,764 of 4,157,543Top 40%
3
Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
8661402 Method and apparatus for AMS simulation of integrated circuit design Chandrashekar L. Chetput, Timothy Martin O'Leary 2014-02-25
8578322 Method and apparatus for AMS simulation of integrated circuit design Chandrashekar L. Chetput, Timothy Martin O'Leary 2013-11-05
8201137 Method and apparatus for AMS simulation of integrated circuit design Chandrashekar L. Chetput, Timothy Martin O'Leary 2012-06-12