PT

Phung Truong

CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
📍 San Jose, CA: #17,604 of 32,062 inventorsTop 55%
🗺 California: #185,134 of 386,348 inventorsTop 50%
Overall (All Time): #1,876,788 of 4,157,543Top 50%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
11156660 In-system scan test of electronic devices Mitchell G. Poplack, Xiaolei Guo, Justin Schmelzer 2021-10-26
10997343 In-system scan test of chips in an emulation system Mitchell G. Poplack, Xiaolei Guo, Justin Schmelzer 2021-05-04