KS

Keyliane da Silva Fernandes Silvano

CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
📍 Belo Horizonte, BR: #105 of 416 inventorsTop 30%
Overall (All Time): #2,474,984 of 4,157,543Top 60%
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Issued Patents All Time

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
11892504 Method and system for debugging metastability in digital circuits Alberto Arias Drake, Bijitendra Mittra 2024-02-06