JG

Jai Bharat Patel Gulabeela

CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
📍 San Jose, CA: #22,480 of 32,062 inventorsTop 75%
🗺 California: #247,236 of 386,348 inventorsTop 65%
Overall (All Time): #3,126,114 of 4,157,543Top 80%
1
Patents All Time

Issued Patents All Time

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
8838430 Detection of memory access violation in simulations Tuay-Ling Kathy Lang, Neeti Khullar Bhatnagar, George F. Frazier, Qizhang Chao 2014-09-16