| 8812889 |
Memory power manager |
Mark Fullerton, Brent Mulholland, Ravi Sreenivasa Setty |
2014-08-19 |
| 8022966 |
Video, audio and graphics decode, composite and display system |
Alexander G. MacInnis, Chengfuh Jeffrey Tang, Xiaodong Xie, Greg A. Kranawetter, Vivian Hsiun +3 more |
2011-09-20 |
| 7848432 |
System and method for efficiently storing macroblocks in SD-RAM |
Lakshman Ramakrishnan, Brian Schoner, Darren Neuman |
2010-12-07 |
| 7515504 |
Phase controlled high speed interfaces |
Lionel J. D'Luna, Mark Chambers, Thomas Hughes, Kwang Young Kim |
2009-04-07 |
| 7430680 |
System and method to align clock signals |
Lionel J. D'Luna, Thomas Hughes |
2008-09-30 |
| 7333390 |
Phase controlled high speed interfaces |
Lionel J. D'Luna, Mark Chambers, Thomas Hughes, Kwang Young Kim |
2008-02-19 |
| 7246341 |
Byte slice based DDR timing closure |
Lionel J. D'Luna, Tom Hughes |
2007-07-17 |
| 7111111 |
Scheme for optimal settings for DDR interface |
Darren Neuman, Jeffrey Fisher, Joshua Stults, Nitin Borle, Kaushik Bhattacharya |
2006-09-19 |
| 6975557 |
Phase controlled high speed interfaces |
Lionel J. D'Luna, Mark Chambers, Thomas Hughes, Kwang Young Kim |
2005-12-13 |
