Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8856559 | Integrated circuit allowing to test a power management unit based on or more conditions and configuring the plurality of pins to operate in normal and test mode | Veronica Alarcon, Love Kothari, Kerry Thompson | 2014-10-07 |
| 8310263 | Control of tristate buses during scan test | Himakiran Kodihalli | 2012-11-13 |
| 8074132 | Protecting data on integrated circuit | Love Kothari | 2011-12-06 |
| 7581150 | Methods and computer program products for debugging clock-related scan testing failures of integrated circuits | — | 2009-08-25 |
| 7558722 | Debug method for mismatches occurring during the simulation of scan patterns | — | 2009-07-07 |
| 7500165 | Systems and methods for controlling clock signals during scan testing integrated circuits | — | 2009-03-03 |
| 7441164 | Memory bypass with support for path delay test | — | 2008-10-21 |
| 7424417 | System and method for clock domain grouping using data path relationships | — | 2008-09-09 |
| 7395468 | Methods for debugging scan testing failures of integrated circuits | — | 2008-07-01 |
| 7131045 | Systems and methods for scan test access using bond pad test access circuits | — | 2006-10-31 |
| 7089471 | Scan testing mode control of gated clock signals for flip-flops | — | 2006-08-08 |
| 7062693 | Methodology for selectively testing portions of an integrated circuit | James D. Sweet | 2006-06-13 |
| 7058868 | Scan testing mode control of gated clock signals for memory devices | — | 2006-06-06 |
| 7032202 | System and method for implementing a flexible top level scan architecture using a partitioning algorithm to balance the scan chains | Xiaodong Xie | 2006-04-18 |
| 6968519 | System and method for using IDDQ pattern generation for burn-in tests | — | 2005-11-22 |
| 6822439 | Control of tristate buses during scan test | Himakiran Kodihalli | 2004-11-23 |