Amar Guettaf has been granted 16 US patents while listed as an inventor at Broadcom . The first was granted in 2004 and the most recent in October 2014. Amar Guettaf ranks #284,196 of 4,157,543 US inventors in our database (top 6.8%). Patent records list Amar Guettaf in Sunnyvale, CA, US.
Patents per Year Patents granted per year, 2004 to 2014 Bar chart with a peak of 5 patents in 2006. peak 5 2004: 1 patents 2004 2005: 1 patents 2005 2006: 5 patents 2006 2008: 3 patents 2008 2009: 3 patents 2009 2011: 1 patents 2011 2012: 1 patents 2012 2014: 1 patents 2014
Issued Patents All Time
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Showing 1–16 of 16 patents
Patent # Title Co-Inventors Date Approx Value ⓘ
8856559 Integrated circuit allowing to test a power management unit based on or more conditions and configuring the plurality of pins to operate in normal and test mode Veronica Alarcon , Love Kothari , Kerry Thompson 2014-10-07
$3,070,000
8310263 Control of tristate buses during scan test Himakiran Kodihalli 2012-11-13
$5,522,000
8074132 Protecting data on integrated circuit Love Kothari 2011-12-06
$4,109,000
7581150 Methods and computer program products for debugging clock-related scan testing failures of integrated circuits — 2009-08-25
$12,423,000
7558722 Debug method for mismatches occurring during the simulation of scan patterns — 2009-07-07
$7,462,000
7500165 Systems and methods for controlling clock signals during scan testing integrated circuits — 2009-03-03
$6,197,000
7441164 Memory bypass with support for path delay test — 2008-10-21
$5,646,000
7424417 System and method for clock domain grouping using data path relationships — 2008-09-09
$8,122,000
7395468 Methods for debugging scan testing failures of integrated circuits — 2008-07-01
$7,071,000
7131045 Systems and methods for scan test access using bond pad test access circuits — 2006-10-31
$6,985,000
7089471 Scan testing mode control of gated clock signals for flip-flops — 2006-08-08
$7,577,000
7062693 Methodology for selectively testing portions of an integrated circuit James D. Sweet 2006-06-13
$19,993,000
7058868 Scan testing mode control of gated clock signals for memory devices — 2006-06-06
$13,696,000
7032202 System and method for implementing a flexible top level scan architecture using a partitioning algorithm to balance the scan chains Xiaodong Xie 2006-04-18
$14,053,000
6968519 System and method for using IDDQ pattern generation for burn-in tests — 2005-11-22
$13,071,000
6822439 Control of tristate buses during scan test Himakiran Kodihalli 2004-11-23
$22,008,000
