Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10253511 | Multi-flex forming system | — | 2019-04-09 |
| 8931753 | Adjustable form panel system and method of forming | — | 2015-01-13 |
| 8651450 | Adjustable and reusable brace, kicker and tie apparatus | — | 2014-02-18 |
| 6505291 | Processor having a datapath and control logic constituted with basis execution blocks | — | 2003-01-07 |
| 6438679 | Multiple ISA support by a processor using primitive operations | — | 2002-08-20 |
| 6327632 | Adaptable I/O pins manifesting I/O characteristics responsive to bit values stored in selected addressable storage locations, each pin coupled to three corresponding addressable storage locations | — | 2001-12-04 |
| 6308254 | Processing instructions of an instruction set architecture by executing hierarchically organized snippets of atomic units of primitive operations | — | 2001-10-23 |
| 6260112 | Register memory linking | — | 2001-07-10 |
| 6216218 | Processor having a datapath and control logic constituted with basis execution blocks | — | 2001-04-10 |
| 6178482 | Virtual register sets | — | 2001-01-23 |
| 6081880 | Processor having a scalable, uni/multi-dimensional, and virtually/physically addressed operand register file | — | 2000-06-27 |
| 6067601 | Cache memory based instruction execution | — | 2000-05-23 |
| 6016539 | Datapath control logic for processors having instruction set architectures implemented with hierarchically organized primitive operations | — | 2000-01-18 |
| 5966529 | Processor having auxiliary operand register file and complementary arrangements for non-disruptively performing adjunct execution | — | 1999-10-12 |
| 5940626 | Processor having an instruction set architecture implemented with hierarchically organized primitive operations | — | 1999-08-17 |
| 5923894 | Adaptable input/output pin control | — | 1999-07-13 |
| 5900025 | Processor having a hierarchical control register file and methods for operating the same | — | 1999-05-04 |
| 5799164 | Method and apparatus for prefetching instructions at an improved rate based on dispatched control transfer instruction states | — | 1998-08-25 |
| 5376829 | High-speed complementary multiplexer | Alan C. Rogers | 1994-12-27 |
| 5021684 | Process, supply, temperature compensating CMOS output buffer | Bhupendra K. Ahuja | 1991-06-04 |