Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12298343 | Method of identifying vulnerable regions in an integrated circuit | Jeremy Bellay, Thomas F. Kent | 2025-05-13 |
| 12260160 | Fabricated layout correlation | Rohan Prabhu, Noah Mun | 2025-03-25 |
| 12229482 | Recovery of a hierarchical functional representation of an integrated circuit | Andrew Elliott, Daniel A. Perkins | 2025-02-18 |
| 11907627 | Fabricated layout correlation | Rohan Prabhu, Noah Mun | 2024-02-20 |
| 11651126 | Recovery of a hierarchical functional representation of an integrated circuit | Andrew Elliott, Daniel A. Perkins | 2023-05-16 |
| 11010519 | Behavioral design recovery from flattened netlist | Andrew Elliott, Daniel A. Perkins | 2021-05-18 |