Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12143259 | Slow drain and congestion spreading detection service | Massarrah N. Tannous, Daniel L. McKay, Erik P. Smith, Jean E. Pierre, Alan Rajapa | 2024-11-12 |
| 8975920 | Programmable transceiver circuit | — | 2015-03-10 |
| 7895559 | Method for designing structured ASICs in silicon processes with three unique masking steps | — | 2011-02-22 |
| 7418692 | Method for designing structured ASICS in silicon processes with three unique masking steps | — | 2008-08-26 |
| 7239177 | High voltage tolerant off chip driver circuit | — | 2007-07-03 |
| 6944843 | Method for providing a cell-based ASIC device with multiple power supply voltages | — | 2005-09-13 |
| 6765245 | Gate array core cell for VLSI ASIC devices | — | 2004-07-20 |
| 5858817 | Process to personalize master slice wafers and fabricate high density VLSI components with a single masking step | — | 1999-01-12 |
| 5504703 | Single event upset hardened CMOS latch circuit | — | 1996-04-02 |
| 4555721 | Structure of stacked, complementary MOS field effect transistor circuits | Claude L. Bertin, Ronald R. Troutman | 1985-11-26 |
| 4467518 | Process for fabrication of stacked, complementary MOS field effect transistor circuits | Claude L. Bertin, Ronald R. Troutman | 1984-08-28 |
| 4418401 | Latent image ram cell | — | 1983-11-29 |