Issued Patents All Time
Showing 1–25 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12360805 | Vectorized scalar processor for executing scalar instructions in multi-threaded computing | Toshio Nagata, Jianbin Zhu | 2025-07-15 |
| 12346248 | Private memory mode sequential memory access in multi-threaded computing | Toshio Nagata, Jianbin Zhu | 2025-07-01 |
| 12253509 | Multiphase flow cylindrical model test system and test method | Qiang Xue, Zhixiang Chen, Yong Wan, Mingli Wei, Jiangshan Li +2 more | 2025-03-18 |
| 12131157 | Mixed scalar and vector operations in multi-threaded computing | Toshio Nagata, Jianbin Zhu, Ryan Braidwood | 2024-10-29 |
| 12093214 | On-chip memory system for a reconfigurable parallel processor | Ryan Braidwood, Jianbin Zhu, Toshio Nagata | 2024-09-17 |
| 11995030 | Reconfigurable parallel processor with stacked columns forming a circular data path | Ryan Braidwood, Jianbin Zhu, Toshio Nagata | 2024-05-28 |
| 11971847 | Reconfigurable parallel processing | Jianbin Zhu | 2024-04-30 |
| 11858017 | In-situ vapor injection thermal desorption device | Qiang Xue, Mingli Wei, Jiangshan Li, Yong Wan, Zhixiang Chen +2 more | 2024-01-02 |
| 11520725 | Performance monitor for interconnection network in an integrated circuit | Xiao Sun | 2022-12-06 |
| 11293869 | Core-shell heterostructures composed of metal nanoparticle core and transition metal dichalcogenide shell | Xinqi Chen, Vinayak P. Dravid | 2022-04-05 |
| 11226927 | Reconfigurable parallel processing | Jianbin Zhu | 2022-01-18 |
| 11214878 | Nanoseed-induced lateral monolayers and vertical wings of transition metal dichalcogenides | Jennifer G. DiStefano, Xinqi Chen, Vinayak P. Dravid | 2022-01-04 |
| 11182336 | Reconfigurable parallel processing with a temporary data storage coupled to a plurality of processing elements (PES) to store a PE execution result to be used by a PE during a next PE configuration | Jianbin Zhu | 2021-11-23 |
| 11182333 | Private memory access for reconfigurable parallel processor using a plurality of memory ports each comprising an address calculation unit | Jianbin Zhu | 2021-11-23 |
| 11182334 | Shared memory access for reconfigurable parallel processor using a plurality of memory ports each comprising an address calculation unit | Jianbin Zhu | 2021-11-23 |
| 11182335 | Circular reconfiguration for reconfigurable parallel processor using a plurality of memory ports coupled to a commonly accessible memory unit | Jianbin Zhu | 2021-11-23 |
| 11176085 | Reconfigurable parallel processing with various reconfigurable units to form two or more physical data paths and routing data from one physical data path to a gasket memory to be used in a future physical data path as input | Jianbin Zhu | 2021-11-16 |
| 10956360 | Static shared memory access with one piece of input data to be reused for successive execution of one instruction in a reconfigurable parallel processor | Jianbin Zhu | 2021-03-23 |
| 10906743 | Roller and locking method thereof | Yue Chen, Fei Zhang, Zhigang Song | 2021-02-02 |
| 10891071 | Hardware, software and algorithm to precisely predict performance of SoC when a processor and other masters access single-port memory simultaneously | Eric Simard, Xiao Sun | 2021-01-12 |
| 10776311 | Circular reconfiguration for a reconfigurable parallel processor using a plurality of chained memory ports | Jianbin Zhu | 2020-09-15 |
| 10776310 | Reconfigurable parallel processor with a plurality of chained memory ports | Jianbin Zhu | 2020-09-15 |
| 10776312 | Shared memory access for a reconfigurable parallel processor with a plurality of chained memory ports | Jianbin Zhu | 2020-09-15 |
| 10733139 | Private memory access for a reconfigurable parallel processor using a plurality of chained memory ports | Jianbin Zhu | 2020-08-04 |
| 10334079 | Orchestrating operations at applications | Daniel T. Travison | 2019-06-25 |