Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12386751 | Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SOC and extensible via cxloverethernet (COE) protocols | Shreyas Shah, Nagarajan Subramaniyan, Jack Regula, Jeffrey Earl | 2025-08-12 |
| 12326813 | Heterogeneous architecture, delivered by cxl based cached switch SOC and extensible via cxloverethernet (COE) protocols | Shreyas Shah, Nagarajan Subramaniyan, Jack Regula, Jeffrey Earl | 2025-06-10 |
| 12259816 | Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SOC | Shreyas Shah, Nagarajan Subramaniyan, Jack Regula, Jeffrey Earl | 2025-03-25 |
| 11989143 | Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SoC | Shreyas Shah, Nagarajan Subramaniyan, Jack Regula, Jeffrey Earl | 2024-05-21 |
| 11947472 | Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SoC | Shreyas Shah, Nagarajan Subramaniyan, Jack Regula, Jeffrey Earl | 2024-04-02 |
| 7653763 | Subsystem boot and peripheral data transfer architecture for a subsystem of a system-on- chip | Mileend Gadkari, Harsimran S. Grewal | 2010-01-26 |
| 7436954 | Security system with an intelligent DMA controller | Peter Nhat Dinh | 2008-10-14 |
| 7349424 | On-chip inter-subsystem communication including concurrent data traffic routing | Mahadev S. Kolluru, Tom Vu | 2008-03-25 |
| 7243179 | On-chip inter-subsystem communication | Mahadev S. Kolluru | 2007-07-10 |
| 7107381 | Flexible data transfer to and from external device of system-on-chip | Jeffrey Earl, Douglas A. Cross | 2006-09-12 |
| 7095752 | On-chip inter-subsystem communication including concurrent data traffic routing | Mahadev S. Kolluru, Tom Vu | 2006-08-22 |
| 7096292 | On-chip inter-subsystem communication | Mahadev S. Kolluru | 2006-08-22 |
| 6677786 | Multi-service processor clocking system | Tore Lennart Kellgren, Harsimran S. Grewal | 2004-01-13 |
| 6247084 | Integrated circuit with unified memory system and dual bus architecture | Peter Baran, Roderick James McInnis | 2001-06-12 |
| 5555433 | Circuit for interfacing data busses | Uoc H. Nguyen, Sam Su, Li-Fung Cheung | 1996-09-10 |
| 5541932 | Circuit for freezing the data in an interface buffer | Uoc H. Nguyen, Sam Su, Li-Fung Cheung | 1996-07-30 |
| 5450547 | Bus interface using pending channel information stored in single circular queue for controlling channels of data transfer within multiple FIFO devices | Uoc H. Nguyen, Lipson Whang | 1995-09-12 |
| 5363485 | Bus interface having single and multiple channel FIFO devices using pending channel information stored in a circular queue for transfer of information therein | Uoc H. Nguyen, Lipson Whang | 1994-11-08 |
| 5335326 | Multichannel FIFO device channel sequencer | Uoc H. Nguyen, Lipson Whang | 1994-08-02 |