| 10747611 |
Safety enhancement for memory controllers |
Alain Vergnes, Marc Maunier |
2020-08-18 |
| 10620881 |
Access to DRAM through a reuse of pins |
Patrick Filippi, Marc Maunier |
2020-04-14 |
| 9372818 |
Proactive quality of service in multi-matrix system bus |
Franck Lunadier, Renaud Tiennot |
2016-06-21 |
| 8468281 |
Apparatus to improve bandwidth for circuits having multiple memory controllers |
— |
2013-06-18 |
| 7739539 |
Read-data stage circuitry for DDR-SDRAM memory controller |
Alain Vergnes |
2010-06-15 |
| 7679987 |
Clock circuitry for DDR-SDRAM memory controller |
Alain Vergnes, Frédéric Schumacher |
2010-03-16 |
| 7539078 |
Circuits to delay a signal from a memory device |
Alain Vergnes, Frédéric Schumacher |
2009-05-26 |
| 7433262 |
Circuits to delay a signal from DDR-SDRAM memory device including an automatic phase error correction |
Alain Vergnes, Frédéric Schumacher |
2008-10-07 |
| 7423928 |
Clock circuitry for DDR-SDRAM memory controller |
Alain Vergnes, Frédéric Schumacher |
2008-09-09 |
| 7269704 |
Method and apparatus for reducing system inactivity during time data float delay and external memory write |
Nicolas Rescanieres, Anne Lafage |
2007-09-11 |