Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12250067 | Precision time protocol with multi-chassis link aggregation groups | Petr Budnik, Avininderpal Singh Grewal | 2025-03-11 |
| 11870555 | VLAN-aware clock synchronization | Harold Fong, Petr Budnik | 2024-01-09 |
| 11502766 | Precision time protocol with multi-chassis link aggregation groups | Petr Budnik, Avininderpal Singh Grewal | 2022-11-15 |
| 11502767 | VLAN-aware clock synchronization | Harold Fong, Petr Budnik | 2022-11-15 |
| 11184097 | VLAN-aware clock hierarchy | Harold Fong, Petr Budnik | 2021-11-23 |
| 11070303 | Management message loop detection in precision time protocol | Avininderpal Singh Grewal, Petr Budnik | 2021-07-20 |