Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12118249 | Memory bank hotspotting | Gregory S. Mathews, Kai Lun Hsiung, Lakshmi Narasimha Murthy Nukala, Shane J. Keil, Thejasvi Magudilu Vijayaraj +1 more | 2024-10-15 |
| 11403037 | Ordering memory requests based on access efficiency | Shane J. Keil, Gregory S. Mathews, Lakshmi Narasimha Murthy Nukala, Thejasvi Magudilu Vijayaraj, Kai Lun Hsiung +1 more | 2022-08-02 |
| 11221798 | Write/read turn techniques based on latency tolerance | Gregory S. Mathews, Kai Lun Hsiung, Lakshmi Narasimha Murthy Nukala, Peter Fu, Rakesh L. Notani +3 more | 2022-01-11 |
| 10872652 | Method and apparatus for optimizing calibrations of a memory subsystem | Rakesh L. Notani, Lakshmi Narasimha Murthy Nukala, Kai Lun Hsiung, Sukalpa Biswas | 2020-12-22 |
| 10734983 | Duty cycle correction with read and write calibration | Robert E. Jeter, Rakesh L. Notani, Kai Lun Hsiung | 2020-08-04 |
| 10678478 | Ordering memory requests based on access efficiency | Shane J. Keil, Gregory S. Mathews, Lakshmi Narasimha Murthy Nukala, Thejasvi Magudilu Vijayaraj, Kai Lun Hsiung +1 more | 2020-06-09 |
| 10545701 | Memory arbitration techniques based on latency tolerance | Gregory S. Mathews, Kai Lun Hsiung, Lakshmi Narasimha Murthy Nukala, Peter Fu, Rakesh L. Notani +3 more | 2020-01-28 |
| 9478263 | Systems and methods for monitoring and controlling repetitive accesses to volatile memory | Bin Ni, Kai Lun Hsiung, Sukalpa Biswas | 2016-10-25 |
| 9384820 | Aligning calibration segments for increased availability of memory subsystem | Neeraj Parik, Thejasvi Magudilu Vijayaraj, Kai Lun Hsiung | 2016-07-05 |