Issued Patents All Time
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6999372 | Multi-ported memory cell | — | 2006-02-14 |
| 6885610 | Programmable delay for self-timed-margin | — | 2005-04-26 |
| 6505225 | Adder logic circuit and processor | — | 2003-01-07 |
| 6343039 | Data transfer circuit | Kenichi Agawa | 2002-01-29 |
| 6289438 | Microprocessor cache redundancy scheme using store buffer | — | 2001-09-11 |
| 6011713 | Static random access memory including potential control means for writing data in memory cell and write method for memory cell | Fumiyuki YAMANE, Tadahiro Kuroda, Masataka Matsui, Yasuo Unekawa, Tetsu Nagamatsu | 2000-01-04 |
| 5715426 | Set-associative cache memory with shared sense amplifiers | Makoto Takahashi | 1998-02-03 |
| 5396448 | Associative memory system with hit entry detection circuit | Masanori Uchida | 1995-03-07 |
| 5317201 | Logical circuit for detecting a potential | — | 1994-05-31 |
| 5287323 | Semiconductor memory device | Makoto Takahashi | 1994-02-15 |
| 5210236 | Differential amplifier | — | 1993-05-11 |
| 5136545 | Semiconductor memory device having a sensitivity controllable sense amplifier circuit | — | 1992-08-04 |